COMPILING ISSUE WITH VHDL

Can anyone help me out compiling VDHL code
"library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity up_counter is
port(pb0, pb1, clk : in std_logic;
Q, q_out, clk_out: out std_logic_vector (3 downto 0));
end up_counter;
architecture sequential of up_counter is
signal count: std_logic_vector(3 downto 0);
begin
process (pb1, clk)
begin
if (pb1 = '1') then
count <= "0000";
elsif (CLK'event and (CLK = '1'))
then
count <= count + "0001";
end if;
end process;
Q <= count;
end sequential;

architecture Behavioral of up_counter is
signal clk_sig : std_logic;
begin
process(pb1,clk)
variable cnt : integer;
begin
if (pb1='0') then
clk_sig<='0';
cnt:=0;
elsif rising_edge(clk) then
if (cnt=24999999) then
clk_sig<=NOT(clk_sig);
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;


clk_out <= clk_sig;


end Behavioral;
""
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