VHDL Port map issue


I'm having an issue regarding portmapping.

I have:
Topcomponent(T) with [b]output[/b] F.

two subcomponents:
S1 with [b]output[/b] Y
S2 with [b]input[/b] G

What i want to do is port map the output Y to the output F and the input G.

Is that doable without making a copy of the output Y withing the component?

Regards Aimo
Sign In or Register to comment.

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!