Need help with som basic VHDL programming

I am trying to build a full adder, by using 2 half adders and a or gate. I know it is possible and my half adders works perfectly, but i don't seem to be able to connect the the right way... here is my current code
my problem is not the understanding on how to build the full adder, my problem is that i haven't been coding in VHDL for more than a few days ;)

Hope someone will take a few mins and help me out ;)

[code]library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port (a, b, cin : in std_logic;
sum, carry_out : out std_logic);
end full_adder;

architecture dataflow_4 of full_adder is
signal i1, i2, i3 : std_logic; -- Husk denne, ellers forst
Sign In or Register to comment.

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!