Vhdl problem : conv_integer

Hi everybody,

I juste started vhl a few days ago and face my first real problem. I don't find how to fix it alone. It comes with the conv_integer function.

CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.


I just try to create a GCD calculator, but my output just stays stuck to 0 all the simulation time. Could you plese help my to solve this issue?

I attach my tb and component code :

[code]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.all;

--------------------------------------------------------------

entity gcd is

port( clk: in std_logic;
rst: in std_logic;
go_i: in std_logic;
x_i: in unsigned std_logic_vector(3 downto 0);
y_i: in unsigned std_logic_vector(3 downto 0);
d_o: out unsigned std_logic_vector(3 downto 0)
);
end gcd;

--------------------------------------------------------------

architecture FSMD of gcd is
begin

process(rst, clk)

-- define states using variable
type S_Type is (ST0, ST1, ST2);
variable State: S_Type := ST0 ;
variable Data_X, Data_Y: unsigned(3 downto 0);

begin
if (rst='1') then -- initialization

d_o(3 downto 0)<= "1111";

State <= ST0;
elsif (clk'event and clk='1') then
case State is
when ST0 => -- starting
if (go_i='1') then
Data_X := x_i;
Data_Y := y_i;
State := ST1;
else
State := ST0;
end if;
when ST1 => -- idle state
State := ST2;
when ST2 => -- computation
if (Data_X/=Data_Y) then
if (Data_X -- go back
d_o <= "1111";
State := ST0;
end case;
end if;

end process;

end FSMD;

--------------------------------------------------------------

[/code]

and here is the testbench :

[code]

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.all;

entity test_GCD is -- entity declaration
end test_GCD;

----------------------------------------------------------------

architecture Bench of test_GCD is

component gcd
port( clk: in std_logic;
rst: in std_logic;
go_i: in std_logic;
x_i: in unsigned std_logic_vector(3 downto 0);
y_i: in unsigned std_logic_vector(3 downto 0);
d_o: out unsigned std_logic_vector(3 downto 0)
);
end component;

signal T_clk,T_rst,T_go_i: std_logic;
signal T_x_i, T_y_i, T_d_o: unsigned std_logic_vector(3 downto 0);

begin

U1: GCD port map(T_clk,T_rst,T_go_i,T_x_i,T_y_i,T_d_o);

Clk_sig: process
begin
T_clk<='1'; -- clock signal
wait for 5 ns;
T_clk<='0';
wait for 5 ns;
end process;

process

variable err_cnt: integer :=0 ;

begin

-- case 1: input 0C & 80, output should be 4
T_rst<='1';
T_go_i<='0';
T_x_i<="1100";
T_y_i<="1000";
wait for 20 ns;

T_rst<='0';
wait for 30 ns;
T_go_i<='1';
wait for 200 ns;
assert(T_d_o=4) report "Error1" severity error;
if (T_d_o/=4) then
err_cnt := err_cnt + 1;
end if;

-- summary of all the tests to see if any error
if (err_cnt=0) then
assert false
report "Testbench of GCD completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;

wait;

end process;

end Bench;

-----------------------------------------------------------------
configuration CFG_TB of test_GCD is
for Bench
end for;
end CFG_TB;
-----------------------------------------------------------------

[/code]

Thanks by advance, sure i'll help you too on this forulm when i will be better :p
Sign In or Register to comment.

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!

Categories