VHDL Simulation

I need to simulate my code in vhdl. Basically, the input is a string of 10 bits. The timing of each bit 52 us. So I need about 0.5 ms of simulation run. I am using graphical testbench of xilinx modelsim. My clock is set for 10 ns. In my testbench I have extended the clock for almost 1 ms. However, when I run the simulation, the simulation runs only for 440 ns and then the clock stops. ANY IDEA HOW TO CORRECT THE PROBLEM ?

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