Quartus is optimizing away too much of my code - Programmers Heaven

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!


Welcome to the new platform of Programmer's Heaven! We apologize for the inconvenience caused, if you visited us from a broken link of the previous version. The main reason to move to a new platform is to provide more effective and collaborative experience to you all. Please feel free to experience the new platform and use its exciting features. Contact us for any issue that you need to get clarified. We are more than happy to help you.

Quartus is optimizing away too much of my code

I need some serious help on this code. I've been tweaking the code for hours and nothing helps. I have a small case statement waiting for a change on an integer signal called index_2. For some reason that integer signal isn't changing, so Quartus removes my case statement from synthesis. What is going wrong? Why does quartus not think that index_2 is used at all?

In the code below I use a module called clk_enabler. That just sends a pulse once every n clock cycles, where n is 5208 for this code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity serial_display is
clock : in std_logic;
four_byte_in : in std_logic_vector(31 downto 0);
bit_out : out std_logic
end entity serial_display;


architecture behv of serial_display is

component clk_enabler is
period: natural
clock: in std_logic;
clear_L: in std_logic;
enable: out std_logic
end component clk_enabler;

signal clk_en_sig_1 : std_logic := '0';
signal current_byte : std_logic_vector(9 downto 0) := "1000000000";

signal index_1 : integer range 0 to 9 := 0;
signal index_2 : integer range 0 to 3 := 0;


CASE index_2 is
when 0 => current_byte(8 downto 1) <= four_byte_in(31 downto 24);
when 1 => current_byte(8 downto 1) <= four_byte_in(23 downto 16);
when 2 => current_byte(8 downto 1) <= four_byte_in(15 downto 8);
when 3 => current_byte(8 downto 1) <= four_byte_in(7 downto 0);
end case;

current_byte <= '1' & current_byte(8 downto 1) & '0';
bit_out <= current_byte(index_1);
end process;

process(clk_en_sig_1, clock)
if rising_edge(clock) and clk_en_sig_1 = '1' then
if index_1 < 9 then
index_1 <= index_1 + 1;
index_1 <= 0;

if index_2 < 3 then
index_2 <= index_2 + 1;
index_2 <= 0;
end if;

end if;
end if;
end process;

enabler: clk_enabler generic map(period=>5208)
port map(clock=>clock, clear_L=>'1', enable=>clk_en_sig_1);

end behv;

Sign In or Register to comment.