VHDL questions - Programmers Heaven

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!


Welcome to the new platform of Programmer's Heaven! We apologize for the inconvenience caused, if you visited us from a broken link of the previous version. The main reason to move to a new platform is to provide more effective and collaborative experience to you all. Please feel free to experience the new platform and use its exciting features. Contact us for any issue that you need to get clarified. We are more than happy to help you.

VHDL questions

Hello. I was wondering how do I import and use an entity I created in one VHD file in another VHD file? What folder do I have to place the file in and how do I reference in the file I need to use it in.

Also, every time I try to put a second entity in a single VHD file I get a weird "out of virtual memory" error.Either tha, or it tells me that STD_LOGIC is reference but not used in the second entity, but not for the first. I tried placing the entities in different order and it is always the second one that throws the error.

Any help would be much appreciated!
Sign In or Register to comment.