Need help with a basic VHDL test bench. - Programmers Heaven

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Need help with a basic VHDL test bench.

I am currently working on a stopwatch in VHDL, and made a counter module. Now I need to make a test bench for this module, and I am simply lost.

[code]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity countermodule is
Port ( reset : in STD_LOGIC_VECTOR (1 downto 0);
startstop : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
Qout1 : out std_logic_vector (3 downto 0);
Qout2 : out std_logic_vector (3 downto 0);
Qout3 : out std_logic_vector (3 downto 0);
Qout4 : out std_logic_vector (3 downto 0));
end countermodule;

architecture Behavioral of countermodule is

component Counter1 is
Port ( res1 : in std_logic_vector (3 downto 0);
en1 : in STD_LOGIC_VECTOR (1 downto 0);
clk : in std_logic;
countout1 : out std_logic_vector (3 downto 0));
end component;

component counter2 is
Port ( res2 : in std_logic_vector (3 downto 0);
en2 : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
countout2 : out std_logic_vector (3 downto 0));
end component;

component counter3 is
Port ( res3 : in std_logic_vector (3 downto 0);
en3 : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
countout3 : out std_logic_vector (3 downto 0));
end component;

component counter4 is
Port ( res4 : in std_logic_vector (3 downto 0);
en4 : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
countout4 : out std_logic_vector (3 downto 0));
end component;

component Counter is
Port ( clk : in STD_LOGIC;
en : in std_logic;
countout : out STD_LOGIC);
end component;
begin


end Behavioral;[/code]

This is the code for my counter module, help will be appreciated.

Best regards

Fupson
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