Type mismatch error in vhdl - Programmers Heaven

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Type mismatch error in vhdl

Greetings! This is my first thread.

I have a package that contains the following type:

[code]type t_rgb_64x48 is array(0 to 47) of std_logic_vector(63 downto 0);[/code]

and is being used in my file.vhd file.


file.vhd contains an entity that contains the type of the package mentioned earlier:

[code]RData_in : in t_rgb_64x48;
ColumnAddress_Start : in integer;
ColumnAddress_End : in integer;
RowAddress_Start : in integer;
RowAddress_End : in integer;[/code]

It also contains a signal with its corresponding type:

[code]type t_vgaram is array(0 to 479) of std_logic_vector(639 downto 0);
signal s_rstorage : t_vgaram;

I need to access s_rstorage through the following statement:

[code]s_rstorage(ColumnAddress_End downto ColumnAddress_Start)
(RowAddress_End downto RowAddress_Start)
<= RData_in(ColumnAddress_End downto
(RowAddress_End downto RowAddress_Start);
to store the value of RData_in to s_rstorage and making sure that they are of the same width in 2D.

The problem is this error:

[code]Type of s_rstorage is incompatible with type of RData_in.[/code]

I know that they have different types as the cause of the error. But how do I fix this problem?
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