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Implementation of Booth

I have a problem with my radix-8 booth vhdl code during synthesis process.can any one help me.


Top-level design

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE work.fun_pkg.ALL;

ENTITY booth_mult8 IS
GENERIC
(
aw: integer := 15;
xw : integer := 7;
pw : integer := 23
);

PORT
(
dat_a : IN std_logic_vector(aw downto 0);
dat_x : IN std_logic_vector(xw downto 0);
dat_out : OUT std_logic_vector(pw downto 0)
);
END booth_mult8;

ARCHITECTURE rtl OF booth_mult8 IS
type ccarr IS array (((xw+2)/3)-2 downto 0) of std_logic_vector(3 downto 0);
type pparr IS array (((xw+2)/3)-2 downto 0) of std_logic_vector(aw+1 downto 0);
type spparr IS array (((xw+2)/3)-2 downto 0) of std_logic_vector(aw+xw+1 downto 0);
SIGNAL inv_dat_a : std_logic_vector(aw downto 0);
SIGNAL inv_dat_3a : std_logic_vector(aw+1 downto 0);
SIGNAL dat_out_sig : std_logic_vector(pw downto 0);
Signal dat_3a: std_logic_vector(aw+1 downto 0);

BEGIN

inv_dat_a <= tc(dat_a); --two's complement of multiplicand
dat_3a <= (dat_a&'0')+('0'&dat_a);-- 3A generation
inv_dat_3a <=tc(dat_3a);-- (-3A) generation

proc_comb : PROCESS(inv_dat_a,dat_3a,dat_a,dat_x)
VARIABLE cc : ccarr;
VARIABLE pp : pparr;
VARIABLE spp : spparr;
VARIABLE prod : std_logic_vector(aw+xw+1 downto 0);
BEGIN
cc(0) := dat_x(2)&dat_x(1)&dat_x(0)&'0';
FOR i in 1 to ((xw+2)/3)-2 LOOP
cc(i) := dat_x(3*i+2)&dat_x(3*i+1)&dat_x(3*i)&dat_x(3*i-1);
END LOOP;
FOR i in 0 to ((xw+2)/3)-2 LOOP
CASE cc(i) IS
WHEN "0001" | "0010" => pp(i) :=dat_a(aw)&dat_a;
WHEN "0011" | "0100" => pp(i) :=dat_a&'0';
WHEN "0111" => pp(i) :=dat_a&"00";
WHEN "1000" => pp(i) :=inv_dat_a&"00";
WHEN "0101" | "0110" => pp(i) :=dat_3a;
WHEN "1001" | "1010" => pp(i) :=inv_dat_a;
WHEN "1011" | "1100" => pp(i) :=inv_dat_a&'0';
WHEN "1101" | "1110" => pp(i) :=inv_dat_a(aw)&inv_dat_a;
WHEN OTHERS => pp(i) := (OTHERS => '0');
END CASE;
FOR j in (aw+2) to (aw+xw+1) LOOP -- sign extend
spp(i)(j) := pp(i)(aw+1);
END LOOP;
spp(i)(aw+1 downto 0) := pp(i);

-- shifting operation
FOR j in 0 to i-1 LOOP
spp(i)(aw+xw+1 downto 3) := spp(i)(aw+xw-2 downto 0);
spp(i)(2 downto 0) := "000";
END LOOP;
END LOOP;
prod := spp(0);
FOR i in 1 to ((xw+2)/3)-2 LOOP
prod := prod + spp(i); -- add partial products to get result
END LOOP;
dat_out_sig <= prod;
END PROCESS proc_comb;

dat_out <= dat_out_sig;

END rtl;

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