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VHDL Problem, Need help!

I'm not long new to VHDL programming, and I've wrote up a multiplexer which takes in 32 bits and releases 8.

This code is as follows:(COMPONENT)

entity Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end Multiplexer32to8;

architecture Behavioral of Multiplexer32to8 is

Signal A, B, C, D, Out_temp : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Wires used to create Input Array

Begin -- Main Body Begins

A <= DataStream (7 downto 0);
B <= DataStream (15 downto 8);
C <= DataStream (23 downto 16);
D <= DataStream (31 downto 24);

process (A, B, C, D, SelectLine)
Begin
Case SelectLine is
when "00" => out_temp <= A;
when "01" => out_temp <= B;
when "10" => out_temp <= C;
when "11" => out_temp <= D;
when others => out_temp <= "ZZZZZZZZ"; -- Return Default added
end case;
end process;

ABCDOut <= out_temp;

end Behavioral;

___________________________________________________________
This part works all in all, its the next part that I can't figure out and would be greatful for the help. I want to generate 6 of these multiplexers, so I wrote this:

entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
ABCDEF: out std_logic_vector(5 downto 0));
end MultiplexerX6;

architecture Behavioral of MultiplexerX6 is [color=Blue]-- Error Here[/color]

component Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);
signal Out_temp : std_logic_vector(5 downto 0);

begin

A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (63 downto 32);
C_temp <= DataStreams (95 downto 64);
D_temp <= DataStreams (127 downto 96);
E_temp <= DataStreams (159 downto 128);
F_temp <= DataStreams (191 downto 160);

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), Out_temp(0)); [color=Red]-- Error here[/color]
B2: Multiplexer32to8 port map(B_temp, SelectLine(3 DOWNTO 2), Out_temp(1)); [color=Red]-- Error here[/color]
B3: Multiplexer32to8 port map(C_temp, SelectLine(5 DOWNTO 4), Out_temp(2)); [color=Red]-- Error here[/color]
B4: Multiplexer32to8 port map(D_temp, SelectLine(7 DOWNTO 6), Out_temp(3)); [color=Red]-- Error here[/color]
B5: Multiplexer32to8 port map(E_temp, SelectLine(9 DOWNTO 8), Out_temp(4)); [color=Red]-- Error here[/color]
B6: Multiplexer32to8 port map(F_temp, SelectLine(11 DOWNTO 10), Out_temp(5)); [color=Red]-- Error here[/color]

ABCDEF <= Out_temp;
end Behavioral;
_________________________________________________________________

The Errors I keep getting are:
HDLCompiler:539 Indexed name is not a std_logic_vector (marked in red)

HDLCompiler:854 Unit behavioral ignored due to previous errors
VHDL file MultiplexerX6.vhd ignored due to errors (marked in blue)

Comments

  • SeanyboySeanyboy Posts: 2Member
    I got it working, it just wouldnt work in Xilinx 10.1 does however work in Altera software package. The program works, madfe some small changes to the code first. So here it is if anyone is interested in the final product:

    entity MUX32to8X6 is
    Port ( DataStreams : in std_logic_vector(191 downto 0);
    SelectLine : in std_logic_vector(11 downto 0);
    AOut: out std_logic_vector(7 downto 0);
    BOut: out std_logic_vector(7 downto 0);
    COut: out std_logic_vector(7 downto 0);
    DOut: out std_logic_vector(7 downto 0);
    EOut: out std_logic_vector(7 downto 0);
    FOut: out std_logic_vector(7 downto 0));
    end MUX32to8X6;

    architecture Behavioral of MUX32to8X6 is

    component MUX32to8 is
    Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
    SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
    ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
    end component;

    signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);

    begin


    A_temp <= DataStreams (31 downto 0);
    B_temp <= DataStreams (63 downto 32);
    C_temp <= DataStreams (95 downto 64);
    D_temp <= DataStreams (127 downto 96);
    E_temp <= DataStreams (159 downto 128);
    F_temp <= DataStreams (191 downto 160);

    B1: MUX32to8 port map(DataStream => A_temp, SelectLine => SelectLine(1 DOWNTO 0), ABCDOut => AOut);
    B2: MUX32to8 port map(DataStream => B_temp, SelectLine => SelectLine(3 DOWNTO 2), ABCDOut => BOut);
    B3: MUX32to8 port map(DataStream => C_temp, SelectLine => SelectLine(5 DOWNTO 4), ABCDOut => COut);
    B4: MUX32to8 port map(DataStream => D_temp, SelectLine => SelectLine(7 DOWNTO 6), ABCDOut => DOut);
    B5: MUX32to8 port map(DataStream => E_temp, SelectLine => SelectLine(9 DOWNTO 8), ABCDOut => EOut);
    B6: MUX32to8 port map(DataStream => F_temp, SelectLine => SelectLine(11 DOWNTO 10), ABCDOut => FOut);


    end Behavioral;

  • abcbatteryabcbattery Posts: 3Member
    This post has been deleted.
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