Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!

Sign In with Facebook Sign In with Google Sign In with OpenID

Categories

We have migrated to a new platform! Please note that you will need to reset your password to log in (your credentials are still in-tact though). Please contact lee@programmersheaven.com if you have questions.
Welcome to the new platform of Programmer's Heaven! We apologize for the inconvenience caused, if you visited us from a broken link of the previous version. The main reason to move to a new platform is to provide more effective and collaborative experience to you all. Please feel free to experience the new platform and use its exciting features. Contact us for any issue that you need to get clarified. We are more than happy to help you.

Need help with som basic VHDL programming

I am trying to build a full adder, by using 2 half adders and a or gate. I know it is possible and my half adders works perfectly, but i don't seem to be able to connect the the right way... here is my current code
my problem is not the understanding on how to build the full adder, my problem is that i haven't been coding in VHDL for more than a few days ;)

Hope someone will take a few mins and help me out ;)

[code]library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port (a, b, cin : in std_logic;
sum, carry_out : out std_logic);
end full_adder;

architecture dataflow_4 of full_adder is
signal i1, i2, i3 : std_logic; -- Husk denne, ellers forst
Sign In or Register to comment.