Universal shift register design (Assignment) - Programmers Heaven

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Universal shift register design (Assignment)

I am trying to finish my assignment on universal shift register but I am always having a syntax error on the begin below the sensetive list. I have tried everything I can do but all effort is in vein, may someone help me fix this problem. i have also put the code which I have written if there are any errors may you help by highlighting them please.

ntity Univeral_shift_reg is
Port ( SIR, SIL, CLK, RST : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Univeral_shift_reg;

architecture Behavioral of Univeral_shift_reg is
signal qtmp: STD_LOGIC_VECTOR (3 downto 0)
Begin
process (CLK, RST)
begin
if (RST = '0') then
qtmp <= (others => '0');
elsif CLK event and CLK = '1' then
if (S = "01") then qtmp <= (SIL & qtmp (2 downto 1));
elsif (S = "10") then qtmp <= (qtmp (1 downto 0)& SIR));
elsif (S = "11") thenb qtmp <= data;
end if
end if;
end process;
end behavioral;
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