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VHDL code HELP ME

help me...
I do a project to university test in vhdl.
I have to make a entity that implement the block phase generator of a DDS with the same features of AD7008 (Analog Devices). To have two different frequency register ( two input port of entity) to do FSK modulation behaving one bit (a inout bit of entity).
The data to two frequency register have to be send through a parallel 32 bit bus.
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