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PIC: STATUS logic


I am programming the PIC16F84 and I don't understand the
following thing.

The MICROCHIP data sheet DS30430C says:
==============================================================
" 4.2.2.1 STATUS REGISTER
...
If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
....
For example, clrf STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged)."
==============================================================

I tried the above example with MPLAB simulator and I confirm
that it is true. See below my eight try:

STATUS before clrf
try 1) 00011000
try 2) 00011001
try 3) 00011010
try 4) 00011011
try 5) 00011100
try 6) 00011101
try 7) 00011110
try 8) 00011111

STATUS after clrf
try 1) 00011100
try 2) 00011101
try 3) 00011110
try 4) 00011111
try 5) 00011100
try 6) 00011101
try 7) 00011110
try 8) 00011111


Then I wanted to clear all the flag Z, DC and C
I thought that the following sequence
"
movlw 0xF8
andwf STATUS
"
is not correct because andwf affects the Z bit and the write
to Z, DC and C is disabled, with Z flag set or cleared
according to device logic.

I checked my statement with MPLAB simulator.
I expected the following results

STATUS before sequence movlw 0xF8, andwf STATUS
try 1) 00011000
try 2) 00011001
try 3) 00011010
try 4) 00011011
try 5) 00011100
try 6) 00011101
try 7) 00011110
try 8) 00011111

STATUS expected after sequence movlw 0xF8, andwf STATUS
try 1) 00011000
try 2) 00011001
try 3) 00011010
try 4) 00011011
try 5) 00011000
try 6) 00011001
try 7) 00011010
try 8) 00011011

The thing that I don't understand is that MPLAB simulator
give me the following results

STATUS from MPLAB simulator after sequence movlw 0xF8, andwf STATUS
try 1) 00011000
try 2) 00011000
try 3) 00011000
try 4) 00011000
try 5) 00011000
try 6) 00011000
try 7) 00011000
try 8) 00011000

I think that it is not correct with respect the general
rule in the data sheet (that is valid for clrf instruction
but not for andwf instruction).

Is my reasoning correct or I don't understand the STATUS
behavior logic ?

Which is the general logic of STATUS register ?

Thanks
Silvano


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