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68k Opcode Sheet

blipblip Member Posts: 756
Could someone please send me a 68k opcodes sheet? I need it because I'm working on _*TRUE*_ processor portability (not the lies C/C++ programmers babble about). So far I have five bytes of hex that allow compatibility between the x86 and z80 (of course, by making them jump to code meant for each).

Thanx in advance!

Comments

  • CytCyt Member Posts: 557
    Sound like an interesting project, although I don't seem to understand if you're actually trying to port machine code betweeen processors???

    You should try to search a bit before asking. A searched on google, and found this after 4 seconds:

    http://vmoc.museophile.com/cards/
    that linked to
    ftp://ftp.comlab.ox.ac.uk/pub/Cards/txt/68000.txt

    I don't know if this is what you're after, but take it or leave it.


  • roland_changroland_chang Member Posts: 27
    : Sound like an interesting project, although I don't seem to understand if you're actually trying to port machine code betweeen processors???
    :
    : You should try to search a bit before asking. A searched on google, and found this after 4 seconds:
    :
    : http://vmoc.museophile.com/cards/
    : that linked to
    : ftp://ftp.comlab.ox.ac.uk/pub/Cards/txt/68000.txt
    :
    : I don't know if this is what you're after, but take it or leave it.
    :
    :
    :

    another one

    http://www.ticalc.org/pub/text/68k/



  • blipblip Member Posts: 756
    Thanx 4 the help, but I already saw these documents (they don't show the mnemonics and hex opcodes side-by-side).
  • CytCyt Member Posts: 557
    [b][red]This message was edited by the Moderator at 2002-5-6 6:27:55[/red][/b][hr]
    : Thanx 4 the help, but I already saw these documents
    : (they don't show the mnemonics and hex opcodes side-by-side).

    That's right. I was a bit too fast on the trigger there.

    But the docs that roland_chang mentions have it:

    http://www.ticalc.org/pub/text/68k/68kpm.zip

    e.g. (qutoing from page 4-73):

    CLR - Clear an Operand - CLR
    (M68000 Family)
    Operation: 0 -> Destination
    Assembler Syntax: CLR < ea >
    Attributes: Size = (Byte, Word, Long)
    Description: Clears the destination operand to zero.
    The size of the operation may be specified as byte, word, or long.
    [code]
    Condition Codes:
    X N Z V C
    - 0 1 0 0

    Instruction Format:
    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    0 1 0 0 0 0 1 0 | SIZE | EFFECTIVE ADDRESS
    MODE | REGISTER
    [/code]
    SIZE:
    Size field - Specifies the size of the operation.
    00 - Byte operation
    01 - Word operation
    10 - Long operation

    etc. etc. etc.

    It's always lengthy to fully document such instructions. Even a simple register clear has 256 different instructions

  • blipblip Member Posts: 756
    Well, I'm not exactly allowed to download ZIPs and so I do so reluctantly or not at all. I'll look into them now, though. :-)
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